The present invention relates to the field of low-power integrated circuits. More particularly, the present invention relates to a CMOS power up circuit that is resistant to drooping on the power supply.
Minimizing any static current is critical in extending operating time in portable or battery power device. Accordingly, the power up circuit, which operates only briefly as power is first applied to the device, should not consume static current after the power up signal has been generated. In addition, it is advantageous to have the ability to tune the threshold of the power up event for different applications. Prior art power up circuits are disclosed in U.S. Pat. Nos. 5,565,807 and 5,617,048. However, these circuits require bipolar/BiCMOS processes for their fabrication. These prior art circuits are configured to use pn diodes as well as Schottky transistors, which are not generally available in a CMOS fabrication process. Additionally, these prior art circuits incur a static current drain. Moreover, if the power supply input of the device droops below a certain level, the power up signal will be reset, causing the device to reset, turn off, or otherwise behave erratically.
Thus, what is required is a power up circuit which is capable of maintaining a valid power up signal, or power up indication, even when the power supply voltage droops below a switch on threshold, in comparison to the prior art. What is required is a power up circuit that maintains a valid power up signal and that can be readily fabricated using modern CMOS VLSI fabrication techniques. In addition, what is required is a solution that can implement power up threshold tuning for the needs of different devices. The present invention provides a novel solution to the above requirements.
Embodiments of the present invention provide a power up circuit which is capable of maintaining a valid power up signal, or power up indication, even when the power supply voltage droops below a switch on threshold. Embodiments of the present invention implement a power up circuit that maintains a valid power up signal and that can be readily fabricated using modern CMOS VLSI fabrication techniques. In addition, embodiments of the present invention implement power up threshold tuning for the needs of different devices.
In one embodiment, the present invention is implemented as a CMOS power up circuit for producing a power up signal for an integrated circuit device. The CMOS power up circuit includes a plurality of transistor chains coupled to first and second select lines. The first and second select lines are configured to enable a selected one of the transistor chains. A VCC input is coupled to the transistor chains. An output latch is included in the power up circuit for generating a power up signal. The output latch is coupled to the transistor chains and to the VCC input and is configured to keep the power up signal deasserted until a voltage from the selected one transistor chain rises past a switch on threshold as VCC rises. When VCC rises past the switch on threshold, the output latch asserts the power up signal and maintains the power up signal asserted at the VCC level, even if the VCC voltage level droops below the switch on threshold.
In one embodiment, each of the plurality of transistor chains is configured to provide a respective switch on threshold by providing a respective resistance when enabled by the first and second select lines. The first and second select lines are configured to implement an adjustable switch on threshold as the first and second select lines selectively enable one of the transistor chains.
In one embodiment, the output latch is configured to use feedback to keep the power up signal deasserted and to maintain the power up signal asserted. The output latch can comprise a first inverter and second inverter coupled to implement the feedback.